1. Field of the Invention
The present invention relates to a data transmission device, and in particular to a data transmission device for use in a computer system and the like.
2. Description of the Prior Art
In a data processing system having a processor, memory unit and data transmission device connected to each other via the same bus lines, in the case where data is processed and produced by the processor and is transmitted to an external portion through the data transmission device, two methods of data transmission have been employed in the prior art.
As the first method of data transmission, the processor transfers the data from the memory to a buffer provided in the data processing system by executing an instruction. In the first method of data transmission, since the processor directly contributes to the data transfer operation, the data processing operation in the processor is interrupted during the transfer operation performed by the processor, resulting in a deterioration of the efficiency of the entire system.
As the second method of data transmission, data is transferred directly from the memory unit to the buffer by a DMA (Direct Memory Access) function provided in the data transmission device when receiving an instruction from the processor. It is noted that the DMA function requires the use of special hardware for the direct transfer of data to or from memory to minimize the interruptions caused by program-controlled data transfers.
FIG. 1 shows a constitution of a conventional data transmission device utilizing the second data transmission method. A data transmission device 51 composed of a parameter memory unit 52 and address generating unit 53, is connected to an external destination 2 through external bus lines 5 for use in common with the processor 3 and memory unit 4.
The operation of the data transmission device utilizing the second method is described below with reference to FIG. 1.
First, a plurality of unprocessed data is read out from the memory 4 and the read out data is processed by the processor 3. The data processed by the processor 3 is written into the memory 4.
Next, the processor 3 sets the parameter memory unit 52 and sends a data transmission starting instruction to the data transmission device 51 for starting data transmission. In the data transmission device 51, an address is produced by the address generator 53 using the storage value of the parameter memory unit 52 set by the processor 3. Subsequently, the data transmission device 51 gains access to the memory unit 4, so that the data read out from the memory unit 4 is transmitted to the external destination 2 through the data transmission device 51.
FIG. 2 shows a timing chart for explaining the operation of the conventional data transmission device shown in FIG. 1. It is assumed that, the data to be transmitted to the external destination 2 consists of three pieces of data D1, D2 and D3 arranged in series in the memory 4; the data D1, D2 and D3 are transmitted in this order, wherein the data D3 is previously stored in the memory 4.
As shown in FIG. 2, in the first processing step 1 the processor 3 reads unprocessed (or not yet processed) data d2 to be processed therein from the memory 4, and in the step 2 the processor 3 processes the data d2 read therein and produces the processed data D2. In the step 3 the processor 3 writes the data D2 into the memory 4. In the steps 4, 5 and 6, in a manner similar to that of steps 1, 2 and 3, unprocessed data d1 is read into the processor 3 and is processed in the processor 3, so that the processed data D1 is produced by the processor 3 and is written into the memory 4. With the completion of the process in the step 6, the processed data D1, D2 and D3 to be transmitted to the external destination 2 are provided in the memory 4 arranged in the order of D1, D2 and D3 in series; the processor 3 sets the value of the data transmission device 51 in the steps 7 and 8, and subsequently the processor 3 transmits the data transmission starting signal to the data transmission device 51 in the step 9.
In the step 10, the processor 3 reads another piece of unprocessed data d4 to be processed therein from the memory 4, and then the data transmission device 51 attempts to gain access to the memory 4 and to read the processed data D1 to be first transmitted. However, since the external bus 5 is being used by the processor 3, the data D1 written in the memory 4 can not be read out by the data transmission device 51.
In the step 11, the unprocessed data d4 is processed by the processor 3 so as to produce the processed data D4 therefrom. Since the processor 3 releases the external bus 5, it becomes possible for the data transmission device 51 to gain access to the memory 4, so that the data D1 is read into the data transmission device 51 and is transmitted to the external destination 2 through the data transmission device 51.
In the step 12, the processor 3 writes the produced data D4 into the memory 4, and subsequently, the data transmission device 51 attempts to gain access to the memory 4 and to read in the data D2 to be transmitted next. However, since the external bus 5 is being used by the processor 3, the data D2 can not be read in the data transmission device 51.
The processes in the steps 13, 14 and 15 and in the steps 16, 17 and 18 are similar to those of steps 10, 11 and 12. In the step 14 the data D2 can be transmitted to the external destination 2, and in the step 17 the data D3 can be transmitted to the external destination 2, whereby the transmission of the data D1, D2 and D3 is completed in the step 17.
However, in such a conventional data processing system, in general, only when the external bus 5 is released from the processor 3, does it become possible for the data transmission device to gain access to the memory to transmit data to an external destination. When the processor releases the bus at a high frequency, in other words, when the frequency of use of the bus for access to the memory is low, since the data is transmitted to the external destination by way of the data transmission device during the period of releasing the bus, the data transmission time overlaps the effective time of the processor to gain access to the memory. On the other hand, when the frequency of use for access to the memory by the processor is such high in such a case where an operation of numeric values is executed so that the bus is not released by the processor, it is difficult to prevent an overlap between the data transmission time and the data processing effective time.